Description:

With the surge in no. of hobbyists using FPGA for their projects, it has become one thing to look out for. MyHDL is python library enabling people to develop simple pythonic code which is lot easier to read and develop than standard Verilog and VHDL languages, that can also be used to program FPGAs. The proposal is to get the audience acquainted with MyHDL, its ease of use and short learning curve, especially from beginners perspective, empowering them to get started implementing real projects in a very quick manner. My GSoC (and my fellow GSoCers) experience developing cores using MyHDL will be used extensively as an example case.

OUTLINE:

• Intro : Who am I?
• Briefing of FPGAs and the standard languages(Verilog and VHDL). (5 min)
• MyHDL briefing. (5 min)
• Difference between general(sequential execution) vs FPGA(parallel execution) programming. (5 min)
• Few FPGA program examples highlighting MyHDL simplicity and ease to learn and use compared to the standard HDL languages. (10 min)
• Present an outline of development stages of a more complex FPGA project using MyHDL using my GSoC experience as an example. (10 min)
• Wrap up and questions if any. (5 min)

Prerequisites:

Python 3.5, Awareness of FPGAs.

Content URLs:

Blogs of ongoing work in GSoC 2016 - https://ravijain056.wordpress.com/category/myhdl/ GEMAC Core developed as part of GSoC 2016 - https://github.com/ravijain056/GEMAC MyHDL Website: http://myhdl.org/

Previous talk on MyHDL by Jan Decaluwe : https://www.youtube.com/watch?v=LSgOpvr8FII

Speaker Info:

Student Pursuing undergraduate degree from SVNIT, Surat. Working for PSF-MyHDL organisation, developing GEMAC core under the program, Google Summer of Code 2016. Previously have taken various seminars/workshops at university level for about 100-200 people on subjects like microcontrollers, advanced electronics, fun physics, etc.

Speaker Links:

https://www.linkedin.com/in/ravijain056