From Python to Silicon

MyHDL is a free, open source Python software package that can take you from Python to silicon! It is both a hardware description language and a verification language. The talk illustrates the wonderful features of MyHDL and Python for generating VHDL and Verilog code, converting a list of signals, doing co-simulation with Verilog, generating test benches with test vectors for VHDL and Verilog, et. al. The built-in simulator runs on top of the Python interpreter, and supports viewing waveforms by tracing signal changes in a VCD file. It is released under the LGPL license.

I would like to illustrate the features of MyHDL with numerous examples, and also highlight on how Python has been used. MyHDL is also being used by university professors to train students in hardware verification. This talk will benefit people who cannot afford to buy development boards, but, are interested in learning hardware simulation and verification. For reference:

http://www.myhdl.org/doku.php/overview

It is good to know the fundamentals of computer architecture before attending this talk.

[Admin: Confirmed talk attendance on phone.]

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